AMD 2027 Chip Supply Plan and TSMC 2nm Demand Surge

AMD plans to substantially increase its chip supply in 2027, CEO Lisa Su said in Taipei on October 6, 2026, as demand for AI hardware continues to outrun what the industry can build. The remarks arrive in the same week that TSMC shares hit a record and Taiwanese press reported that several of the foundry's biggest customers had raised their 2nm orders. Together they point to a theme that matters more than any single product launch: advanced foundry capacity, not chip design, is increasingly the pacing item for AI.

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What Lisa Su said about AMD 2027 chip supply

According to Reuters, Su made the comments in Taipei during a visit to Taiwan that included a meeting with Foxconn and planned meetings with TSMC and the memory makers Samsung and SK Hynix. Reuters quoted her as saying: "We've been able to increase our supply as we've gone through 2026, and we're going to substantially increase our supply in 2027."

Asked about demand, she said there is "very, very high demand for the next several years" and that "we need more advanced wafer capacity," per the same Reuters report. Other outlets covering the trip, including Finimize, reported that she described AMD as supply constrained, including on memory, and said the company "could definitely use more." Those additional phrases come from secondary coverage, so treat their exact wording with a little more caution than the Reuters quotes.

TrendForce News added a planning detail from the visit: capacity decisions that once looked one to two years ahead now extend three, four or even five years, because wafer fabrication, advanced packaging and substrates all have to be ready at the same time. It also reported that Su said AMD's previously announced investment of more than $10 billion in Taiwan remains on track.

Why capacity, not demand, is the constraint

AMD's order book is not the open question. Our earlier coverage of AMD's Advancing AI 2026 event, in AMD Advancing AI 2026: MI450, Helios and the Nvidia challenge, listed roughly 14 gigawatts of GPU commitments from OpenAI, Meta and Anthropic. Filling those commitments depends on three things arriving together: leading-edge wafers, advanced packaging such as CoWoS, and high-bandwidth memory.

Per TrendForce, AMD began production of its MI450-series platform in mid-2026 on TSMC's 2nm node with CoWoS packaging, and the MI455 series is scheduled to enter production in early 2027. That sequencing explains why Su's language is about supply rather than demand. A step-change in shipped units in 2027 requires wafer starts to be reserved well before the product ships, which is why planning horizons have stretched.

The 2nm order picture

On September 28, Blockonomi, citing Taiwanese publication EDN, reported that Apple, Nvidia, AMD, Qualcomm and MediaTek had raised their orders for TSMC's 2nm family by 10% to 20%. This is a press report, not a TSMC disclosure, and TSMC does not publish customer-level order data.

The same coverage said the market had originally expected TSMC's 2nm-family capacity at about 90,000 to 100,000 wafers per month by the end of 2026, rising to 110,000 to 140,000 by 2027. A separate TrendForce report on September 14, citing Economic Daily News, put the targets at 90,000 wafers per month at end-2026 and 110,000 by mid-2027, a 22% increase. The same report cited 3nm at more than 180,000 wafers per month at end-2026 and 210,000 by mid-2027, and CoWoS at about 130,000 per month at end-2026, doubling to 260,000 by end-2028.

Estimates differ by source, and some earlier reports gave higher end-2026 figures, so the safest reading is a range rather than a point. The relevant comparison is the growth rate against the order increase: a 22% capacity rise from end-2026 to mid-2027 sits alongside customer orders reportedly 10% to 20% higher. If both reports are right, the extra orders absorb a large share of the added capacity.

2nm ramp economics

A new node follows a recognisable curve. Our coverage of TSMC's Q2 2026 results noted that N2 contributed about 3% of wafer revenue in its first quarter of meaningful sales. Early in a node's life, yields and tool counts limit output, and the earliest wafers go to customers willing to pay for performance per watt. As yields mature, the node spreads from flagship phone chips to AI accelerators and server CPUs.

For AMD the node matters in two places. Its 6th Gen EPYC "Venice" server CPU is built on 2nm, and MI450-series parts mix 2nm and 3nm chiplets, per AMD's product materials covered in our earlier post. Because AMD, Apple and Nvidia are all bidding for the same wafers, a customer cannot simply buy its way out of a shortage: capacity at a given node is added in discrete fab phases, each taking years to plan.

Packaging adds a second bottleneck. TrendForce reported that Su said AMD is exploring other packaging approaches, including fan-out panel-level packaging with Taiwan's supply chain, while still viewing CoWoS as important. That is a hedge against packaging being the limiting step, not a statement that CoWoS is being replaced.

What to watch in TSMC's October 15 results

TSMC reports third-quarter results on Thursday, October 15, according to Taipei Times and other coverage. Shares closed at a record NT$2,575 on October 5 and TSMC accounts for roughly 41% of the TAIEX weighting, so expectations are high. Items worth checking:

• N2 revenue share. The Q2 figure was about 3%. A visibly higher share would show the ramp tracking the order reports.
• Capital expenditure guidance. Larger spending would be consistent with added 2nm and packaging capacity; flat guidance would raise questions about the 2027 targets.
• Commentary on tightness. Whether management describes 2nm and CoWoS as sold out or balanced is the cleanest read on whether Su's supply plan has room to execute.
• Fourth-quarter guidance. Revenue and gross margin guidance show how fast new capacity converts into sales and how it dilutes margins early in a node's life.

What remains unknown

Su did not give unit volumes, and "substantially" is not a number. Whether AMD's supply increase is limited by wafers, packaging, substrates or memory will only show up in shipments through 2027. The order increases come from press reports and may be revised. Memory supply, which Su reportedly flagged as a constraint, sits outside TSMC entirely.

For teams building on AI models, the practical implication is that hardware availability shapes which models are priced attractively and where they run. That is one reason model-agnostic tools such as Metir, which let you switch between providers rather than depend on one supply chain, can be a sensible hedge.

Sources:

• AMD plans to substantially increase supply in 2027, CEO says (Reuters via Investing.com)
• AMD's Lisa Su visits TSMC, AI supply chain partners (TrendForce News, Oct 6, 2026)
• AMD says AI demand is outrunning chip supply (Finimize)
• TSMC reportedly targets 22% 2nm, 16% 3nm capacity boost by mid-2027 (TrendForce News, Sept 14, 2026)
• Taiwan Semiconductor stock climbs as major clients boost 2nm chip orders (Blockonomi, Sept 28, 2026)
• TAIEX hits record high, rising 2.55% (Taipei Times, Oct 6, 2026)

Image credits

• In-body: Lisa Su speaking at SXSW 2024 (a 2024 photo, not from the October 2026 remarks). Photo by Fuzheado, Wikimedia Commons, CC BY 4.0.
• Hero: TSMC Global R&D Center at dusk, illustrative only. Photo by 曾 成訓, Wikimedia Commons, CC BY 2.0.