OLIX Raises $312M to Build AI Chips That Compute With Light

On August 3, 2026, OLIX, a London-based chip startup, announced a $312 million Series B at a $3.3 billion valuation, described across the coverage as Europe's largest-ever semiconductor funding round. That is a striking amount of capital for a company that has not shipped a chip. It is also, on its own terms, a bet on a specific and testable idea: that the thing holding back AI inference today is not raw compute, but the electrical wiring and memory that feed it, and that replacing electrons with photons in the right places can loosen that constraint. OLIX calls its chips Optical Tensor Processing Units, or OTPUs, and its first product, DX-1, is aimed squarely at the most memory-hungry part of running a large language model: generating the words, one token at a time.

What OLIX actually builds

OLIX was founded in 2024 under the name Flux Computing and rebranded to OLIX in January 2026, shortly before this raise and its earlier February 2026 Series A of $220 million at a $1 billion valuation. The company's premise is that a single monolithic chip trying to do everything in an AI accelerator is the wrong shape for inference. Instead, OLIX designs dedicated, specialized accelerators for individual stages of token generation and links them with what it describes as a "slow and wide" proprietary photonic interconnect, moving data between chips as light through optical channels rather than as electrical signals over copper. The pitch is that this lets each chip be optimized narrowly for the computational step it actually performs, while the optical fabric between them avoids the bandwidth and power penalties that come with moving large volumes of data electrically over any real distance.

The first product built on this architecture is DX-1, an accelerator aimed at the decode stage of LLM inference for models above roughly 100 billion parameters. OLIX says the design targets throughput above 10,000 tokens per second per user with better throughput-per-watt than incumbent approaches, and, notably, it uses SRAM instead of high-bandwidth memory (HBM), the stacked DRAM that sits on essentially every modern AI accelerator. That single design choice, dropping HBM, is the most consequential thing about DX-1, and it only makes sense once you separate the two stages that make up how a language model actually produces an answer.

Prefill and decode are different problems

Every request to a large language model passes through two distinct phases. Prefill is when the model ingests the prompt: it processes potentially thousands of input tokens largely in parallel, building up the internal state (the key-value cache) it will need to generate a response. This phase is compute-bound. The chip is busy doing matrix multiplication, and its arithmetic throughput is what limits how fast prefill finishes.

Decode is the opposite. Once the model starts generating, it produces exactly one new token at a time, and each new token depends on the one before it. There is very little parallel arithmetic to exploit; the accelerator instead spends most of its cycles reading and re-reading model weights and the growing key-value cache from memory. This is why decode is described as memory-bound rather than compute-bound: the ceiling on how fast a model can generate text is set less by how many floating-point operations a chip can do per second and more by how quickly it can move data in and out of memory, over and over, for every single token.

That distinction is the whole logic behind OLIX's SRAM bet. HBM offers enormous capacity and, moving in bulk, high bandwidth, which is exactly what prefill wants. But decode's access pattern is small, sequential, and latency-sensitive, repeated billions of times, and HBM's own bandwidth advantage is harder to fully exploit under that kind of traffic. SRAM, built directly into the logic die, offers far lower latency and higher effective bandwidth for exactly this kind of access, at the cost of much lower capacity per unit of chip area and higher cost per gigabyte. OLIX's bet is that for a chip whose only job is decode, that trade is worth making, and that a photonic interconnect stitching several SRAM-equipped decode chips together can supply enough aggregate capacity to serve genuinely large models without ever touching HBM.

Why avoiding HBM matters right now

This is not just an engineering preference; it is a supply-chain and cost decision made at a specific moment. Through 2026, the AI industry has been living through what we've covered as an AI memory supercycle: HBM has been reported to earn memory makers several times more revenue per wafer than standard DDR5, and the three companies that control nearly all global DRAM production have been redirecting wafer capacity toward it, at the direct expense of ordinary RAM supply and pricing. HBM allocation has consequently become one of the tightest bottlenecks in AI hardware, with the leading memory makers' HBM output reported booked out years in advance. A chip architecture that needs none of it sidesteps that queue entirely. Whether that turns out to be foresight or a necessity born of not being able to secure HBM allocation as a new entrant, the practical effect is the same: OLIX is proposing to scale a decode accelerator using a memory technology that is not currently the subject of a global shortage.

The investors and the sovereign-semiconductor angle

The round's investor list is as notable as its size. New backers Fundomo, Arm, and Hudson River Trading joined the UK government's Sovereign AI venture fund, with angel participation from Reed Hastings, the Netflix co-founder. Existing investors increased their commitments in the round as well. OLIX also added Professor Nick McKeown to its board, a Stanford professor emeritus and 2025 Marconi Prize recipient who co-founded the networking chip companies Nicira and Barefoot Networks, both later acquired.

A UK sovereign fund taking a position in a domestic chip startup, alongside Arm, itself a British semiconductor company, reads as a deliberate piece of industrial policy. Europe has watched the AI compute buildout concentrate overwhelmingly in the United States and, to a lesser extent, China, largely on the strength of Nvidia's accelerators and TSMC's manufacturing. A homegrown inference-chip company reaching a $3.3 billion valuation, and doing so in a round billed as the continent's largest-ever semiconductor raise, is the kind of data point that governments pursuing "sovereign AI" capability point to. It does not change the underlying manufacturing reality, since OLIX, like every fabless chip designer, still depends on foundries outside Europe to actually produce its silicon, but it does concentrate more of the design, IP, and economic upside of an AI chip company inside the UK than has been typical so far in this cycle.

The risks that keep this pre-revenue

None of this should be read as a settled outcome. OLIX is, by its own funding timeline, a company that will not deliver its first chip to customers until the second half of 2027, roughly a year and a half from this raise. Several distinct risks sit between the money and that delivery date.

Photonic computing itself is a technology with a long history of research promise and a much shorter history of commercial deployment at scale. Optical interconnects already exist in data centers for pure data transport, but building chips where light does more of the actual computational and memory-access work, rather than just carrying signals between conventional silicon, is a much harder engineering problem, and OLIX would be among the first to ship it commercially at this scale if DX-1 arrives on schedule.

Manufacturing and yield are the next hurdle. Photonic components integrate imperfectly with standard CMOS processes, and combining specialized optical elements with conventional logic on a single platform, at a foundry, in volume, has tripped up prior photonic computing efforts. OLIX's stated H2 2027 target for customer deliveries assumes that this integration goes to plan; delays in tape-out, packaging, or yield are the most common way ambitious chip timelines slip.

Software ecosystem risk is arguably the least discussed but most durable obstacle. Every AI accelerator eventually has to run somebody's inference framework, and the incumbent's advantage there is enormous. Nvidia's CUDA software stack has a decade-plus head start, and the model-serving frameworks the industry has standardized on are tuned first, and often only, for Nvidia's memory and interconnect assumptions. A chip that structurally departs from HBM and monolithic GPU design, however sound the hardware argument, still has to convince model providers and inference platforms to build and validate a new software path around it. That is a slower, less capital-intensive problem than fabricating a chip, but it has stalled well-funded chip challengers before.

Finally, there is the ordinary risk of any pre-revenue hardware company: a $3.3 billion valuation prices in a specific, favorable version of the next eighteen months. If DX-1's real-world throughput or cost-per-token advantage turns out to be narrower than advertised once it faces production workloads, or if HBM supply eases as new fab capacity comes online, some of the urgency behind the SRAM-first pitch could soften.

What this means beyond OLIX

The specific numbers here matter less than what they signal about where chip investors think the next constraint sits. For most of the current AI buildout, the scarce resource has been framed as raw accelerator supply, then as power, then as HBM itself. OLIX's raise is a bet that the interconnect and memory architecture around inference, not just the transistor count inside a single chip, is where the next several years of hardware differentiation will actually happen. Teams building AI products sit downstream of all of this: as the underlying hardware layer keeps reshaping itself around bottlenecks like this one, keeping the option to route inference across whichever provider and model stack is most efficient at a given moment, rather than committing to one vendor's hardware assumptions, is the practical hedge, which is part of the case for a model-agnostic workspace like Metir AI.

Whether photonic decode accelerators become a meaningful share of AI inference hardware by 2028, or end up as one of several promising architectures that never cleared the manufacturing and software-ecosystem bar, is genuinely unresolved. What is not in question is that a UK government fund, Arm, a major quantitative trading firm, and a Netflix co-founder collectively decided $312 million was a reasonable price to find out.

Sources:

• Chip startup OLIX raises $312m at $3.3bn valuation, backed by UK govt Sovereign AI venture fund | DatacenterDynamics
• OLIX Raises $312M for Photonic AI Inference, Adds Nick McKeown to Board | ConvergeDigest
• UK chip startup OLIX lands $312 million Series B at $3.3 billion valuation | Yahoo Finance
• OLIX Raises $312M for Photonic AI Chip That Ditches HBM, Britain's Biggest Semiconductor Bet | Tech Times
• Company raises Series B | OLIX
• The 2026 AI Memory Supercycle: Why RAM Prices Are Surging | Metir AI

Image credits

Header image: a 300mm silicon photonics wafer under studio light, by Ehsanshahoseini via Wikimedia Commons, licensed under CC BY-SA 4.0. This is a general silicon photonics wafer, not OLIX's own hardware; no photograph of OLIX's DX-1 chip currently exists. In-body photograph: a sample of colored optical fibers, the physical medium that carries data as light, by Cjp24 via Wikimedia Commons, licensed under CC BY-SA 4.0.