Positron AI Raises $875M to Bet Commodity Memory Beats HBM

Positron AI, a Reno, Nevada based chipmaker building silicon exclusively for AI inference, announced on September 9 and 10, 2026 that it raised $875 million in total funding at a $5 billion post-money valuation. The round is unusual not just for its size but for the specific technical bet behind it: instead of chasing the same High-Bandwidth Memory (HBM) that Nvidia, AMD and every other accelerator maker depends on, Positron is building its next chip around commodity LPDDR5X, the memory type found in phones and laptops. The pitch is that inference, unlike training, is bottlenecked less by raw compute and more by how efficiently a chip moves data, and that a chip built around cheap, abundant memory can win on cost and availability even if it never matches the raw bandwidth of HBM-based rivals.

NVIDIA

The round, in structure

The $875 million is not one check. It breaks into a $375 million Series C priced at a $3.5 billion pre-money valuation, co-led by NEA, Atreides Management, Valor Equity Partners, Andra Capital and SemiAnalysis Capital, plus a follow-on Series C-1 of up to $500 million anchored by NEA and Netscape co-founder Jim Clark. Combined, that produces the $5 billion post-money figure Positron is citing publicly.

The company says the proceeds will fund the tapeout of its next chip, Asimov, on TSMC's N3P process, the production ramp of an inference system called Titan, and a 2 megawatt-plus engineering data center and emulation platform. Asimov is scheduled to tape out at the end of 2026, with production targeted for the second half of 2027, meaning the chip that anchors this valuation will not ship for close to a year from the announcement.

Why inference is a memory problem, not just a compute problem

To understand why a memory choice can carry an $875 million round, it helps to separate two phases of running a large language model. Training a model is compute-heavy: it involves dense matrix multiplications across huge batches of data, and more FLOPS reliably means faster training. Inference, particularly the token-by-token generation that dominates real-world usage, works differently. To produce each new token, the chip has to read the model's entire set of weights, often tens or hundreds of gigabytes, from memory. That read happens for every single token generated, which means the ceiling on how fast a chip can generate text is often set by how quickly and how completely it can move data out of memory, not by how many arithmetic operations its cores can theoretically perform.

This is the reasoning behind describing inference as "memory-bound." A GPU can have enormous theoretical compute capacity and still sit idle waiting on memory if its memory subsystem cannot keep pace with the read pattern that inference demands. That gap between a chip's peak advertised bandwidth and the bandwidth it actually achieves on a real inference workload is what Positron is targeting when it talks about utilization.

The core claim, and why it needs a caveat

Positron says Asimov, which pairs its compute architecture with 288 GB to 2,304 GB of LPDDR5X memory per chip depending on configuration, achieves greater than 90 percent memory-bandwidth utilization on inference workloads, compared with less than 30 percent for typical GPUs. That is a striking gap if it holds, since it would mean Positron's architecture wastes far less of its available bandwidth than the industry standard.

It is important to be precise about what this number is and is not. It is Positron's own reported figure, describing a chip that has not taped out yet and will not reach production until the second half of 2027. No independent benchmark of Asimov exists, because no Asimov silicon exists. The claim is a thesis the company is asking investors, and eventually customers, to underwrite well ahead of proof. Whether a commodity-memory architecture can sustain that utilization advantage at production scale, against whatever Nvidia and its rivals ship in the same window, is genuinely unresolved. Nothing here should be read as evidence that Positron's chip outperforms Nvidia's; it should be read as a specific, falsifiable bet that will be tested when the hardware ships.

The tradeoff Positron is making

The reason commodity memory is worth the bet at all comes down to supply and packaging. HBM is manufactured by a small number of suppliers, requires advanced packaging techniques like TSMC's CoWoS to attach to a compute die, and has been in a persistent supply crunch as AI accelerator demand has outstripped capacity. LPDDR5X, by contrast, is produced at enormous volume for phones, laptops and other consumer electronics, giving it a fundamentally different cost and supply profile. The tradeoff is that LPDDR5X offers lower peak bandwidth per pin than HBM, which is why HBM became the default choice for accelerators in the first place.

Positron's bet is that architecture and utilization can compensate for lower peak bandwidth, and that the resulting cost and capacity advantages matter more for inference than for training. This is also a well-timed argument: HBM has reportedly been sold out well into 2027, so a design that sidesteps that shortage entirely has an obvious appeal to buyers who cannot get allocation regardless of price.

Where this fits in the broader market

Positron is one of a growing group of challengers, alongside companies like Groq, Cerebras and SambaNova, building chips specifically for inference rather than adapting training hardware. That focus reflects a real shift in industry spending, as the volume of inference workloads running in production has grown to rival or exceed training spend at many labs and enterprises. A $5 billion valuation for a company whose flagship product will not ship until mid-to-late 2027 is a wager that this shift toward specialized, cost-optimized inference silicon has room to support more than one winner, and that commodity memory specifically is a differentiated enough angle to carve out share against Nvidia's dominant position.

For teams building AI products today, the more durable lesson is not about picking a winner between HBM and LPDDR5X architectures, but about the pace of change in the underlying hardware layer. New accelerator designs, each with different cost and performance profiles for different workloads, are arriving faster than any single deployment decision can keep up with. That is part of the case for staying flexible about where and how a workload actually runs. Metir AI applies the same model-agnostic principle at the software layer, routing each task to whichever leading model fits it best rather than locking a workflow to one provider, so that shifts happening underneath, in silicon or in model pricing, do not require re-architecting anything on top.

The takeaway

Positron AI's $875 million raise is a bet on a specific, testable idea: that commodity memory, paired with the right architecture, can serve inference workloads more efficiently than the HBM-based designs that dominate today's accelerator market. The claimed utilization numbers are compelling on paper, but they describe a chip that has not been built yet, and the real test comes only when Asimov tapes out at the end of 2026 and reaches production in the second half of 2027. Until then, the honest framing is that Positron has raised a very large amount of money to prove a thesis, not to report a result.

Sources:

• Positron AI Raises $875 Million at a $5 Billion Valuation to Bring Its Next-Generation Inference Silicon to Market | PRNewswire
• Chipmaker Positron nabs $875M to speed up inference with consumer-grade memory | SiliconANGLE
• Positron AI's $875M bet: commodity memory could break Nvidia's inference lock | Forkast
• Positron AI Raises $875M to Prove Commodity Memory Can Beat HBM in Inference | TechTimes
• Positron AI Raises $875M, Asimov Inference Silicon | Converge Digest

Image credits

A 300mm silicon wafer (representative), Peellden, via Wikimedia Commons, licensed under CC BY-SA 3.0.