GPT-Synopsys: OpenAI's AI Model for Chip Design Explained

On September 30, 2026, OpenAI and Synopsys announced GPT-Synopsys, a specialized model meant to reason about chip design and verification and to directly operate Synopsys' electronic design automation (EDA) tools. The announcement matters less as a product launch, which has no stated date, than as a test of whether AI agents can handle one of the most tool-heavy workflows in engineering.

What OpenAI and Synopsys announced

According to the Synopsys press release, the two companies signed a multi-year strategic agreement. OpenAI will license Synopsys' EDA tools to develop the model, the companies plan joint go-to-market work, and The Decoder reports the arrangement includes revenue sharing. No financial figures were disclosed.

Other stated details:

GPT-Synopsys will run on OpenAI-hosted infrastructure.
It is designed to integrate with customer agent systems and the Synopsys.ai Autopilot platform.
Customer data is not used to train the model and is encrypted at rest and in transit.
Early technology engagements are underway with leading semiconductor customers, who were not named.

Synopsys CEO Sassine Ghazi said the agreement will expand access to Synopsys' design capabilities. OpenAI President Greg Brockman said the work would help engineers "explore more designs and get to a working chip faster."

Sept 30, 2026Announcement date

Multi-yearAgreement term

Revenue shareBetween OpenAI and Synopsys

UndisclosedFinancial terms and launch date

Why EDA is a hard domain for AI agents

Chip design is not a single prompt and answer. It is a chain of specialized tools, each producing long reports that a human reads before changing an input and running the tool again. An agent has to do the same: operate the tool, interpret the output, decide what to change, and repeat. That tool-use loop is what the announcement describes, with engineers delegating objectives and reviewing outputs.

Two features make this harder than most agent work:

Long cycles. A synthesis, place-and-route or verification run is not instant, so each iteration is expensive and an agent cannot cheaply guess its way to an answer.
Competing goals. Chip designers trade off power, performance and area (PPA) while closing timing and verification. Improving one number often worsens another.

Where a tool-operating model slots into the flow

Every stage is a loop: run a tool, read a long report, change an input, run again. A failure late in the flow can send work back to an earlier stage.

Stage 1
RTL and architecture
Design entry
Agent loop
Draft and revise RTL against a spec
Stage 2
Functional verification
Simulation, formal
Agent loop
Write tests, read failures, patch RTL
Stage 3
Logic synthesis
Design Compiler class
Agent loop
Tune constraints, read PPA reports
Stage 4
Place and route
Fusion Compiler, Innovus class
Agent loop
Adjust floorplan, rerun, compare PPA
Stage 5
Timing and power signoff
PrimeTime class
Agent loop
Triage violations, apply fixes, recheck
Stage 6
Physical verification
Calibre class
Agent loop
Clear rule violations before tape-out

Illustrative. Stages follow the standard flow; agent loops are analysis, not a published GPT-Synopsys specification.

The diagram above is illustrative. Its stages follow the standard flow described in SemiAnalysis' EDA primer, which names synthesis, place and route, signoff timing and physical verification as distinct tool categories. The agent loops are our analysis of where a tool-operating model could fit, not a published GPT-Synopsys specification.

Close view of a silicon wafer showing a grid of repeated integrated circuit dies — A silicon wafer carries a grid of identical dies. Every die starts as a design that passes the tool flow above. Photo by Le hollandais volant, CC BY 4.0.

The EDA market structure

EDA is concentrated. SemiAnalysis puts the market at roughly $18 billion in 2025, with Synopsys, Cadence and Siemens EDA holding more than 85% combined. It also credits Synopsys with 84% to 85% of synthesis and more than 90% of signoff timing, while Siemens' Calibre is effectively required by foundries for physical verification.

Reported scale confirms the picture. Synopsys posted fiscal 2025 revenue of $7.054 billion, of which Ansys contributed $756.6 million after the $35 billion acquisition closed on July 17, 2025. Cadence reported fiscal 2025 revenue of $5.297 billion and a $7.8 billion backlog.

$7.054BSynopsys FY2025 revenue

$5.297BCadence FY2025 revenue

$35BSynopsys-Ansys deal, closed July 2025

~$18BEDA market, 2025 (SemiAnalysis)

This structure explains the deal shape. The incumbent owns the tools and the workflow knowledge, while OpenAI brings the model. SemiAnalysis also notes licensing is shifting from seats toward token and capacity models, which would suit usage-driven AI tooling.

AI designing the chips AI runs on

There is a loop here. OpenAI is also working with Broadcom on AI-specific chips, so a model that speeds chip design could shorten the path to more AI hardware. Brockman framed it as "a path to better chips and better AI." Whether the model delivers measurable gains in PPA or verification closure is unproven, since no benchmarks or customer results have been published.

Vertical models as a trend

GPT-Synopsys fits a broader pattern: general frontier models paired with domain tools and domain data, sold with the incumbent software vendor. The trade-off is familiar to anyone choosing between models. A specialized model can be better inside one workflow, while a general one covers more tasks, which is why platforms such as Metir keep several models available rather than committing to one.

What to watch

Named customers and published PPA or verification results.
Availability and pricing, neither of which has been announced.
Whether Cadence and Siemens EDA respond with their own model partnerships.

Sources:

Image credits

Header image: Synopsys headquarters, Mountain View, by User:LPS.1, via Wikimedia Commons, CC0.
Silicon wafer: "Silicon wafer close view" by Le hollandais volant, via Wikimedia Commons, licensed under CC BY 4.0.