Celero Communications announced a $275 million Series C on September 8, 2026, alongside what it calls the first validation of a 2nm coherent digital signal processor with advanced analog technology. The Irvine startup says the silicon is a foundation for 1.6-terabit and later 3.2-terabit optical links in large AI data centers.
Why AI clusters need more optical bandwidth
AI accelerators only deliver useful work when they can move parameters, activations, and results quickly enough across the network. As clusters span more racks, buildings, and campuses, electrical links become harder to extend without rising power and signal-loss costs. Optical transceivers convert electrical data into light for the fiber portion of that path.
A coherent DSP is the signal-processing engine inside certain optical systems. It encodes information onto light, then helps the receiver recover it after transmission has added noise and distortion. Celero's pitch is that moving this processing and its analog circuitry to a 2nm manufacturing process can improve bandwidth density and power efficiency enough to make coherent technology practical deeper inside AI infrastructure.
What Celero validated, and what remains
The company says it successfully validated DSP processing and advanced analog technology on 2nm silicon. That is an engineering milestone, but it is not the same as a commercially qualified transceiver shipping in hyperscale volume. Product integration, packaging, thermal behavior, yields, customer testing, and manufacturing readiness still determine whether a validated chip becomes deployed infrastructure.
Celero's claimed coherent roadmap
The validated 2nm DSP is the common foundation; product readiness and customer deployment remain ahead.
Source: Celero Communications, September 8, 2026. Roadmap does not imply commercial shipment.
The distinction matters because competitors are also moving quickly. Marvell has announced its own 2nm coherent DSP portfolio and a 1.6T ZR/ZR+ pluggable system, while Qualcomm describes a broader 800G and 1.6T connectivity roadmap using PAM4 and coherent-lite approaches. Celero's announcement therefore demonstrates entry into an important technical race, not exclusive ownership of 2nm coherent networking.
Why the funding round is unusually large
Celero was founded in 2024 by engineers from Marvell, Inphi, Broadcom, and ClariPhy. The Series C brings total funding to $415 million and values the company above $3 billion. Atreides Management, Valor Equity Partners, and CapitalG led the round, with Sutter Hill Ventures and Maverick Silicon also participating.
The Series C supplies two thirds of Celero's capital to date
US dollars, millions, announced September 8, 2026.
Source: Celero Communications Series C announcement. Valuation reported above $3 billion.
The capital is intended for research, product development, and production readiness. That last category explains much of the scale. Advanced semiconductor companies must fund design teams, software, verification, tape-outs, packaging, and supply commitments long before customer revenue proves the business.
The demand thesis is broad. McKinsey estimates global data centers could require nearly $7 trillion of investment by 2030, with roughly $5.2 trillion related to AI workloads. That estimate covers far more than optics, but it explains why investors are backing suppliers that may remove a bottleneck inside the buildout.
How to evaluate the Celero 2nm DSP claim
Three milestones will matter more than the financing headline. First is a complete product specification with measured power, reach, error performance, and bandwidth density. Second is evidence of customer qualification, ideally across more than one hyperscaler or module partner. Third is repeatable high-volume manufacturing with acceptable yields.
Until those appear, the correct reading is balanced. Celero has validated an advanced piece of silicon and raised enough capital to attempt commercialization in a market that clearly needs more bandwidth. It has not yet shown that its architecture wins on total system cost or ships at scale. In AI infrastructure, moving data is becoming almost as strategically important as computing it, and the optical layer is where that constraint is increasingly visible.
Sources:
- Celero Communications raises $275 million and validates 2nm coherent DSP silicon | Celero
- The $7 trillion data center build-out | McKinsey
- Marvell 1.6T pluggable and 2nm coherent DSP portfolio | Marvell
- Qualcomm Dragonfly data center connectivity roadmap | Qualcomm
Image credits
Header and in-body photograph: OUSENT bidirectional SFP optical transceivers via Wikimedia Commons, licensed under CC BY-SA 4.0. The image was visually reviewed before use and illustrates the hardware category, not Celero's product.